News
New DRAM circuit design approach for gigabit-era DRAM Hitachi, Ltd., in cooperation with Elpida Memory, Inc. announced that they have developed a new methodology for memory-array design, Concordant Memory Design Using Statistical Integration, which gathers statistics on device parameters from each memory cell on the chip for an accurate distribution of memory-cell characteristics, and applies the results to the quantitative evaluation of the memory array. Technology scaling at the gigabit-era introduces large fluctuations in device parameters that seriously degrade DRAM circuit performance, and it will become increasingly difficult to design a high performance circuit using conventional design methods. The concordant technique developed provides a design guideline in achieving required levels of circuit performance and will be indispensable tool for designing high-quality gigabit-era DRAM.
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